A Practical Approach for IP Integration and V...

A Practical Approach for IP Integration and Validation of an Soc

Author Name : Sobhiraj N., Jobin Cyriac

ABSTRACT

This article discusses the verification process involved in System on Chip (SoC) Application-Specific Integrated Circuit (ASIC) design. Verification ensures that the product meets specified requirements and detects any discrepancies between actual and expected outcomes. The verification process involves testing the ASIC design to confirm its functionality, including performance, power, and timing requirements, and compliance with design specifications. This article outlines the different phases of verification, including module-level verification, system-level testing, coverage analysis, linting, netlist simulation, annotated simulation, and FPGA validation. The article highlights the significance of verification in improving product quality, reducing the risk of failure, and saving time and costs associated with redesigning and retesting the product. FPGA validation is a critical step in verifying ASIC design functionality and performance before committing to fabrication. By implementing an ASIC design on an FPGA, designers can identify any design errors or bugs, reduce the likelihood of major changes or large errors in the silicon area, and increase their confidence in the design implementation.

Keywords: System on Chip (SoC), Application-Specific Integrated Circuit (ASIC), Linting.