Clock Skew Unidirectional Flow Method for ASI...

Clock Skew Unidirectional Flow Method for ASIC Design Implementation

Author Name : Nitin Kumar Suyan, Sunil Kumar Khinchi

DOI: https://doi.org/10.56025/IJARESM.2021.94212974

ABSTRACT

In a sequential circuit, Timing is the main concern of a digital design engineer. As technology is moving into smaller node and demand for a high performance system keep pushing the clock frequency into GHz region, the conventional method of achieving the required timing target is no longer efficient. The conventional method of synthesis, assume ideal clock network as clock tree in not build yet. This approach of ideal clock network is too optimistic which result in data path optimization for setup violation. In this paper a common hierarchy clock skew unidirectional flow method is proposed which help in reducing the number of buffer required in clock tree synthesis stage which results in overall reduction in clock tree power consumption. The overall runtime, power and area are also improved compare to the conventional flow which results in better utilization at timing closure.

Keywords— Application Specific integrated circuit, Flip flop, Clock, Placement and Routing, Design Compiler, Hardware Descriptive Language, Placement and Routing, Static Timing Analysis.