Design and Implementation of UART (Universal ...

Design and Implementation of UART (Universal Asynchronous Receiver Transmitter) Protocol Using System Verilog

Author Name : Mrs. V. Uma, G. Sai Sandeep Kumar, Sk. Gouse Basha, N. Sreenivasa Sai Reddy

ABSTRACT

This paper proposes, a UART (Universal Asynchronous Receiver Transmitter) are described, which is basically a serial data transmission protocol used in digital circuit applications. The architecture of the UART transmitter has a baud rate generator, parity generator, transmitter finite state machine (FSM) and parallel in serial out (PISO). UART receiver has a baud rate generator, negative edge detector, parity checker, receiver finite state machine (FSM) and serial in parallel out (SIPO) register. The baud rate generator of both transmitter is the same, so the baud rate of transmitter/receiver is the same. Baud rate generator is the same as the frequency divider circuit. The data frame of the UART transmitter is 1 start bit, 8 transmits data bits, 1 parity bit and 1 stop bit.

Keywords: UART, PISO, SIPO, FSM, data frame, parity generator or checker, baud rate.