FPGA Implementation of 64-Bit Vedic Multipl...

FPGA Implementation of 64-Bit Vedic Multiplier for Mac Unit

Author Name : V. Moshe Rani, M. Thambi Joseph, D. Manikantha, A. Srikanth, Y. Danush, V. Vamsikrishna

ABSTRACT Multiplication is the almost simplest operation that serves a great purpose in the design of high-speed digital logic systems, digital signal processors or even communication systems. The major limitations that should be focused on the design stage itself are effects of delay and power dissipated. Vedic Mathematics is an ancient system of Mathematics contains 16 Sutras based on which different calculations can be performed. The work has established practicality of Urdhva Triyagbhyam Vedic method for multiplication which is quite different from the repeated addition approach towards multiplication in its process. It allows intermediate products to be generated simultaneously and does not require needless multiplication steps by zeros. The 64-bit MAC or multiply-accumulate unit is a computational unit that has 64-bit input numbers and performs both multiplication and addition on the two inputs. Usually, the unit comprises a multiplier, an adder and a storage register to hold intermediate calculations. This unit is widely used in digital signal processing (DSP) tasks, such as: image processing, filtering and any other task that requires vector dot products and matrix multiplications. The 64-bit MAC unit possesses features making it able to perform highly precise calculations at very low latency and high throughput such that it is versatile enough for performing a number of tasks that require signal processing efficiently.