Implementation of a 32-Bit RISC-V Processor u...

Implementation of a 32-Bit RISC-V Processor using a FPGA

Author Name : Digvijay Dessai, Dr. Nitesh Guinde

DOI: https://doi.org/10.56025/IJARESM.2022.1062197

ABSTRACT

As the demand for increased computation power rises, the legacy processors find themselves incapable of matching the requirements. The RISC-V has been deemed as one of the possible solutions for this problem. Introduced in 2010 at University of California, Berkeley, the RISC-V is an open standard instruction set architecture (ISA) based primarily on the RISC principles. In addition to being devoid of any licensing and royalty fees, the RISC-V is power efficient and has broad industry support and applications in many existing and upcoming domains. Popularly termed as the ‘ Linux of processors ’, the RISC-V has broken down barriers in the semiconductor industry bringing together different companies and industries for open collaboration. The combination of a modular technical approach with an open licence business model will make the RISC-V ubiquitous in the near future and will enable developers of all scales to build and contribute freely thereby paving the way for the next 50 years of computing design and innovation.In this paper, a design of a 32-bit single cycle RISC-V processor has been implemented and realised using verilog and a FPGA. The proposed design was able to implement and execute the basic R-type instructions which have been defined in the RISC-V ISA.

Keywords: RISC-V, instruction set architecture (ISA), Verilog, FPGA, R-type Instructions