Low Power 18-Transistor Fully Static Contenti...

Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 50-nm CMOS

Author Name : Rashmi Shrivastava, Ashish Duvey

ABSTRACT

The design of sequential elements for Near-threshold computing (NTC), as well as in voltage-scaled systems operating at both near-threshold and super-threshold, has not been extensively studied. However, it is well known that sequential elements have a strong sensitivity to process variations in NTC, which can have a significant impact on system yield and power consumption. In order to achieve reliable energy-efficient operation across a wide operating voltage range, a flip-flop should have the following attributes: contention-free transitions, single-phase clocking, which avoids toggling of internal clock inverters and the corresponding power penalty. This paper presents a new flip-flop, referred to as static single-phase contention free flip-flop (S2CFF) that meets the requirements above: it is static, completely contention-free, and uses single-phase clocking. It has the almost same device count as a TGFF, with layout size increase that corresponds to a one poly-pitch increase in 50nm technology.

Keywords: Flip-Flops, static single-phase contention free flip-flop (S2CFF), transmission gate flip-flop(TGFF) ,Low structure reduction scheme , Near-threshold computing (NTC), high speed, Micro wind, DSCH.