RISC-V Processor with Flexible Pipeline using...

RISC-V Processor with Flexible Pipeline using Vedic Multiplier

Author Name : Aashrithest H G, Dr. Ohileshwari M S

ABSTRACT The RISC-V processor is an instruction set which is an open source and allows custom-made based on the modernday needs of computing structures. This paper introduces a flexible 5- stage pipeline 32-bit RISC-V processor using Verilog with Vedic multipliers. This design is based on the RISC-V instruction set architecture (ISA), where the pipeline phase includes instruction fetch, instruction decision, execution, memory access, and write-back. Like signal processor, graphics processor. As the requirement for high speed, low latency, low power consumption and less space increases, new technologies are in high demand. Vedic multipliers, based on Vedic mathematics, are now under scrutiny due to their high-speed and low-energy focus, although some competitions such as the Gathering have shown some improvement in these qualities. Vedic Multiplier technology is used to speed up the multiplication of large numbers. It is on the basis of UrdhvaTriyakbhyam, one from the 16 Vedas used by ancient Indian masters, recently discovered by the Vedas. Multiplication is an important hardware module in modern technologies such as machine learning, deep learning, and signal processing. The processor is synthesized using Cadence Genus tools to analyze the design and key features such as power, area and propagation delay and simulated using Xilinx Vivado.