Safety and Reliability Measures for RISC-V Us...

Safety and Reliability Measures for RISC-V Using Lockstep Model

Author Name : N. Rafkhana, Jayaram K, Shan. N, Jayan M C, Sheeja P George

ABSTRACT

RISC-V provides flexibility to customize the processor for safety critical requirements. To ensure safety, depend ability, and availability, fault tolerance is a requirement for safety- critical systems. Lockstep is a fault tolerant mechanism that detects or recovers transient faults inside a processor. This work proposes a Dual Core Lockstep (DCLS) system for open-source processor architecture RISC-V, using Mi-V core. The same set of application is executed on two identical systems in DCLS, separated by a known delay. When a processor is interrupted, an error is created, then lockstep error detection takes place and a system reset is initiated. This is implemented using liberoSoC Smart Design tool and simulated using Models in pro. Fault injection results indicate that the system effectively detects faults at the output.

Index Terms—ISC-V, Safety critical application, Fault tolerance, Reliability, Dual Core Lockstep ISC-V, Safety critical application, Fault tolerance, Reliability, Dual Core Lock step R