State of the Art in Unified Test bench Design...

State of the Art in Unified Test bench Design for Efficient Co-Simulation and Emulation in Multi-Robot and Ai Accelerator Systems

Author Name : Ankit Chandankhede

ABSTRACT The advancement in robotic systems and AI accelerators demands highly efficient verification processes due to their complexity and the need for rapid development cycles. Traditional methods involve separate testbenches for simulation and emulation, leading to increased maintenance efforts and extended verification timelines. This paper explores the state-of-the-art in unified testbench design, facilitating efficient co-simulation and emulation for multi-robot systems and AI accelerators. By leveraging SystemVerilog and recent support from Synopsys ZeBu, a single testbench can cater to both simulation and emulation needs, thereby reducing development time and resource usage. The approach includes optimizing transaction transfers through a transaction layer using DPI, prefetching data to enhance bandwidth efficiency, and consolidating transactors to minimize pin usage and board requirements. This unified methodology not only streamlines the verification process but also enhances the debugging and functional coverage, leading to higher reliability and performance in robotic and AI systems.