Techniques for Minimizing Power in VLSI Circu...

Techniques for Minimizing Power in VLSI Circuits

Author Name : Halmandge Aishwarya B, Doreen Belinta A, Krishnaveni Cherukuri, Savan Siddharth Ithagani, Dr. Brintha Therese A

Power consumption is a critical challenge in Very-Large-Scale Integration (VLSI) design, with implications for performance, thermal management, and overall energy efficiency in modern electronic systems. This paper provides a comprehensive review of advanced techniques aimed at reducing power dissipation in VLSI circuits. We categorize power reduction strategies into static and dynamic approaches. Static techniques include Dynamic Voltage Scaling (DVS) and Adaptive Voltage Scaling (AVS), which optimize power consumption by adjusting supply voltage according to workload demands. We also examine threshold voltage modification and power gating strategies to mitigate leakage currents and reduce static power loss. On the dynamic front, we analyse techniques such as clock gating to minimize unnecessary switching activity, Dynamic Voltage and Frequency Scaling (DVFS) to balance performance and power consumption, and operand isolation to curtail switching activity in inactive regions. The paper provides an in-depth understanding of some power reduction methods, and their potential for future advancements in power-efficient VLSI design. This paper proposes a novel hybrid approach that combines selective adiabatic logic with non-volatile SRAM (NV-SRAM) for dynamic and leakage power optimization.