VLSI Implementation of 64-Bit Booth Multiplie...

VLSI Implementation of 64-Bit Booth Multiplier for High Speed and Low Latency

Author Name : Niraj Kumar Singh, Prof. Rahul Shrivastava

ABSTRACT The arithmetic logic unit (ALU) is key part of the any processor. The improvement is needed in the ALU for the advanced processor application. Digital multiplier is one of the key operations of the ALU of processor. The Xilinx seven series logic FPGA VLSI processor are using under 5G constraints. Research are continue going on various existing multipliers for enhancing in terms of performance improvement like high speed, low delay, low area, low power etc. This paper proposed low latency VLSI implementation of booth multiplier for FPGA applications. Simulation is done using Xilinx ISE software. Simulation results shows that the performance improvement in terms of speed and latency.