VLSI Implementation of Kogge-Stone Adders

VLSI Implementation of Kogge-Stone Adders

Author Name : Prof. P. P. Gaikwad, Dr. P. N. Shinde, Abhishek Ghogare, Vishal Bhosale, Saurabh Jadhav

ABSTRACT : In the relentless pursuit of ever-faster and more power-efficient electronic devices, the realm of Very-Large-Scale Integration (VLSI) design stands at the forefront. At the heart of these systems lie adders, the fundamental building blocks for arithmetic operations. This paper navigates the intricate landscape of VLSI implementation, spotlighting the Kogge-Stone Adders (KSAs) with a focus on 4-bit and 8-bit architectures. Embraced within the parallel prefix adder family, KSAs usher in a new era of computational efficiency, leveraging their parallel carry propagation mechanism to outshine conventional Ripple Carry Adders (RCAs) in speed and power consumption. Through an indepth exploration of the KSA architecture, this paper meticulously dissects the design intricacies inherent in 4-bit and 8-bit implementations, unveiling their unparalleled advantages while navigating potential limitations. By juxtaposing KSAs against other adder architectures, this study illuminates their transformative potential in the VLSI domain.