Design of 4:1 Multiplexer Based Adder Using V...

Design of 4:1 Multiplexer Based Adder Using Various Logic Techniques

Author Name : M. Sahinippiriya, B. Mary Amala Jenni, P. Yuvarani

ABSTRACT

In recent trends, low power consumption and high speed has become an important consideration while designing any computational devices. Thus designing a circuit with high speed and with less number of transistors are the real challenges in VLSI. This paper introduces varying techniques for designing high speed 4:1 Multiplexer (MUX) based adder. The multiplexer is designed with different logic styles such as Pass Transistor Logic, Transmission Gate Logic and GDI technique  and finally, using the design a 1 bit full adder is designed and the results are being calculated. This paper thus presents, speedy and efficient multiplexer for low power applications like  telecommunication system, computer memory etc. Simulations were performed using Tanner Tool(S-edit, Tspice, and W-edit) 250nm technology.

Keywords: Pass transistor logic, Transmission gate logic , GDI technique, 4:1 Multiplexer, Tanner EDA.