Design of 4-Bit Parallel Shift Register Using...

Design of 4-Bit Parallel Shift Register Using Power Saving Dual Edge D Flip-Flop

Author Name : Damera Bharath Kumar, Sudhir Dakey

ABSTRACT In modern digital design, the demand for high-speed and low-power flip-flops has lead to the exploration of various clocking schemes and transistor technologies. This paper presents the design and implementation of a dual-edge triggered flip-flop using True Single-Phase Clocking (TSPC) in 45nm technology utilizing Cadence Virtuoso. The dual-edge triggered flip-flop captures data on both the rising and falling edges of the clock signal, there by doubling the data throughput without increasing the clock frequency. The modified dual edge D flip flop is designed using CADENCE tool with CMOS 45nm technology.