High-Performance Multiplexer For Power-Aware ...

High-Performance Multiplexer For Power-Aware And Area-Constrained Systems

Author Name : Dr. S. Rama Devi, M.V.L. Akshaya, M. Akhila, D. Mahitha, Md. Waheeda and R. Sruthi

ABSTRACT In VLSI design, minimizing power dissipation and reducing transistor count remain key objectives. This study presents a comparative analysis of various logic families—including Efficient Charge Recovery Logic (ECRL), 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Modified PFAL (MPFAL), Gate Diffusion Input (GDI), and Modified GDI (MGDI)—to evaluate their suitability in digital circuit implementation. Utilizing these logic styles, we have designed a 32:1 multiplexer and conducted extensive simulations using Tanner EDA at the 0.25µm (250nm) CMOS technology node. The results demonstrate that MGDI logic surpasses its counterparts in terms of transistor efficiency, operational speed, and power-delay product (PDP). This work confirms MGDI as the most effective logic style for optimizing both power consumption and area utilization in VLSI circuits, offering practical design strategies for engineers seeking high-performance, low-power digital systems.