Low Power Hybrid Full Adder Using XOR/XNOR Ga...

Low Power Hybrid Full Adder Using XOR/XNOR Gate

Author Name : Venkatesan K, Durai Raj S, Arunkumar B

Abstract

In now days, Increased usage of electronic devices are designed with longer battery life, higher speed and more reliability. The power consumed by the full adder is therefore reduced by optimizing the design XOR-XNOR gates. Simulation results are performed in tanner tool .Four hybrid full adder circuits using new XNOR, XOR gates are proposed in this paper. These circuits are designed to have high speed and less power consumption compared to existing circuits. This is possible due to low output capacitance. Each one of the proposed full adder circuit has its own advantages of speed, power consumption and driving ability. From results, proposed circuits are found to be better than existing circuits. The novel structures of XOR - XNOR gate are proposed for the design of hybrid full adders with low power, high speed and less PDP. The proposed hybrid full adder has superior speed against other full adder circuits with less number of transistors.                                          

Index Terms: FS XOR-XNOR, FS –GDI, Full Adder, Multiplier, MUX, GDI