Smart Hang Detector for Pre-Silicon Environme...

Smart Hang Detector for Pre-Silicon Environment

Author Name : Ankit Chandankhede

ABSTRACT Architectural complexity among products such as Graphics processing unit, Network on chips and AI accelerators has exponentially increases due to newer complex features and multiple instances of pipelines and cores are instantiated. In order to stress verify these complex features and pipeline, long running and extensive are regressed. These testcases can hit the design bugs which can be exposed due to back pressuring or concurrent scenarios. Bugs can cause a testcase to run longer than expected due to endless loop or multiple polling scenarios until a particular condition is met. Such conditions should be detected or avoided in short period of time as compute resources, memory requirements and potentially debug such conditions with proper logging. This can be achieved with proposed hang detector in this paper. Proposed hang detector not only uses idle or not done signals for the unit but also incorporates most important signals to detect the hangs and provides comprehensive information based off signals used in hang detector